并行CRC电路的形式化设计

2023 5th International Conference on Electronic Engineering and Informatics (EEI) Pub Date : 2023-06-30 DOI:10.1109/EEI59236.2023.10212772

Yuchen Nie, Fangfei Cai, Keran Zhang, Sheng Zhong, Hangzai Luo

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引用次数: 0

摘要

循环冗余码(CRCs)用于检测存储和通信系统中的突发错误。本文分析了轨道交通的理论原理和并行轨道交通结构。此外，本文还提出了一种并行CRC的设计方法，该方法可以生成不同并行位宽、不同CRC生成多项式、不同输入数据长度的并行CRC电路。我们的方法的FPGA性能(LUT消耗和最大频率)与最先进的并行CRC方法相当。本文对并行CRC电路的设计具有一定的参考价值。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Formal Design of Parallel CRC Circuit

Cyclic Redundancy Codes (CRCs) are useful to detect burst errors in storage and communications systems. This paper analyzes the theoretical principle of CRC and the parallel CRC structure. Besides, this paper proposes a design method for the parallel CRC, which can generate parallel CRC circuits with different parallel bit width, different CRC generating polynomial, and different input data length. The FPGA performance (LUT consumption and max frequency) of our approach is comparable to the state-of-art parallel CRC method. This paper may be useful for parallel CRC circuit design.

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来源期刊

2023 5th International Conference on Electronic Engineering and Informatics (EEI)

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