Ryuji Yamashita, Sagar Magia, T. Higuchi, Kazuhide Yoneya, T. Yamamura, Hiroyuki Mizukoshi, S. Zaitsu, Minoru Yamashita, Shunichi Toyama, Norihiro Kamae, Juan Lee, Shuo Chen, Jiawei Tao, William Mak, Xiaohua Zhang, Ying Yu, Yuko Utsunomiya, Yosuke Kato, Manabu Sakai, Masahide Matsumoto, H. Chibvongodze, Naoki Ookuma, Hiroki Yabe, Subodh Taigor, Rangarao Samineni, T. Kodama, Y. Kamata, Y. Namai, Jonathan Huynh, Sung-En Wang, Y. He, T. Pham, V. Saraf, Akshay Petkar, Mitsuyuki Watanabe, Koichiro Hayashi, Prashant Swarnkar, H. Miwa, Adit Pradhan, Sulagna Dey, Debasis Dwibedy, Thushara Xavier, Muralikrishna Balaga, Samiksha Agarwal, Swaroop Kulkarni, Zameer Papasaheb, Sahil Deora, Patrick Hong, Meiling Wei, G. Balakrishnan, Takuya Ariki, Kapil Verma, C. Siau, Yingda Dong, Ching-Huang Lu, Toru Miwa, F. Moogat
{"title":"11.1采用64字行层bic技术的512Gb 3b/cell闪存","authors":"Ryuji Yamashita, Sagar Magia, T. Higuchi, Kazuhide Yoneya, T. Yamamura, Hiroyuki Mizukoshi, S. Zaitsu, Minoru Yamashita, Shunichi Toyama, Norihiro Kamae, Juan Lee, Shuo Chen, Jiawei Tao, William Mak, Xiaohua Zhang, Ying Yu, Yuko Utsunomiya, Yosuke Kato, Manabu Sakai, Masahide Matsumoto, H. Chibvongodze, Naoki Ookuma, Hiroki Yabe, Subodh Taigor, Rangarao Samineni, T. Kodama, Y. Kamata, Y. Namai, Jonathan Huynh, Sung-En Wang, Y. He, T. Pham, V. Saraf, Akshay Petkar, Mitsuyuki Watanabe, Koichiro Hayashi, Prashant Swarnkar, H. Miwa, Adit Pradhan, Sulagna Dey, Debasis Dwibedy, Thushara Xavier, Muralikrishna Balaga, Samiksha Agarwal, Swaroop Kulkarni, Zameer Papasaheb, Sahil Deora, Patrick Hong, Meiling Wei, G. Balakrishnan, Takuya Ariki, Kapil Verma, C. Siau, Yingda Dong, Ching-Huang Lu, Toru Miwa, F. Moogat","doi":"10.1109/ISSCC.2017.7870328","DOIUrl":null,"url":null,"abstract":"High floating-gate (FG) to FG coupling and lithography limitations have been preventing 2D-NAND flash from further reduction in die size, (e.g., there is no ISSCC paper discussing a 3b/cell 2D-NAND after 2013 [1,2]). Alternatively, since high-density multi-stacked 3D-flash was first introduced as BiCS flash [3], recent dramatic innovations in 3D-flash technologies are rapidly boosting bit density by increasing the number of stacked layers. The first 3b/cell 3D-flash used 32 layers in 2015 [4], and reached 48 layers in 2016 [5]. Also, density as high as 2.62 and 4.29Gb/mm2 [5,6] were achieved, as shown in Fig. 11.1.7. This rapid scaling of 3D-flash technologies is possible since it is free from the lithography limitation mentioned above. This paper describes a 512Gbit 3b/cell flash fabricated with a 64-word-line-layer BiCS technology. In this work, we implemented three technologies: (1) four-block even-odd-combined row decoding to effectively address the increase of stacked layers; (2) unselected string pre-charge operation to improve endurance and reliability, and; (3) shielded BL current sensing to enhance read throughput. Figure 11.1.1 shows the die photo and the summary of key features.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"31","resultStr":"{\"title\":\"11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology\",\"authors\":\"Ryuji Yamashita, Sagar Magia, T. Higuchi, Kazuhide Yoneya, T. Yamamura, Hiroyuki Mizukoshi, S. Zaitsu, Minoru Yamashita, Shunichi Toyama, Norihiro Kamae, Juan Lee, Shuo Chen, Jiawei Tao, William Mak, Xiaohua Zhang, Ying Yu, Yuko Utsunomiya, Yosuke Kato, Manabu Sakai, Masahide Matsumoto, H. Chibvongodze, Naoki Ookuma, Hiroki Yabe, Subodh Taigor, Rangarao Samineni, T. Kodama, Y. Kamata, Y. Namai, Jonathan Huynh, Sung-En Wang, Y. He, T. Pham, V. Saraf, Akshay Petkar, Mitsuyuki Watanabe, Koichiro Hayashi, Prashant Swarnkar, H. Miwa, Adit Pradhan, Sulagna Dey, Debasis Dwibedy, Thushara Xavier, Muralikrishna Balaga, Samiksha Agarwal, Swaroop Kulkarni, Zameer Papasaheb, Sahil Deora, Patrick Hong, Meiling Wei, G. Balakrishnan, Takuya Ariki, Kapil Verma, C. Siau, Yingda Dong, Ching-Huang Lu, Toru Miwa, F. Moogat\",\"doi\":\"10.1109/ISSCC.2017.7870328\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"High floating-gate (FG) to FG coupling and lithography limitations have been preventing 2D-NAND flash from further reduction in die size, (e.g., there is no ISSCC paper discussing a 3b/cell 2D-NAND after 2013 [1,2]). Alternatively, since high-density multi-stacked 3D-flash was first introduced as BiCS flash [3], recent dramatic innovations in 3D-flash technologies are rapidly boosting bit density by increasing the number of stacked layers. The first 3b/cell 3D-flash used 32 layers in 2015 [4], and reached 48 layers in 2016 [5]. Also, density as high as 2.62 and 4.29Gb/mm2 [5,6] were achieved, as shown in Fig. 11.1.7. This rapid scaling of 3D-flash technologies is possible since it is free from the lithography limitation mentioned above. This paper describes a 512Gbit 3b/cell flash fabricated with a 64-word-line-layer BiCS technology. In this work, we implemented three technologies: (1) four-block even-odd-combined row decoding to effectively address the increase of stacked layers; (2) unselected string pre-charge operation to improve endurance and reliability, and; (3) shielded BL current sensing to enhance read throughput. Figure 11.1.1 shows the die photo and the summary of key features.\",\"PeriodicalId\":269679,\"journal\":{\"name\":\"2017 IEEE International Solid-State Circuits Conference (ISSCC)\",\"volume\":\"118 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"31\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE International Solid-State Circuits Conference (ISSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2017.7870328\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2017.7870328","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology
High floating-gate (FG) to FG coupling and lithography limitations have been preventing 2D-NAND flash from further reduction in die size, (e.g., there is no ISSCC paper discussing a 3b/cell 2D-NAND after 2013 [1,2]). Alternatively, since high-density multi-stacked 3D-flash was first introduced as BiCS flash [3], recent dramatic innovations in 3D-flash technologies are rapidly boosting bit density by increasing the number of stacked layers. The first 3b/cell 3D-flash used 32 layers in 2015 [4], and reached 48 layers in 2016 [5]. Also, density as high as 2.62 and 4.29Gb/mm2 [5,6] were achieved, as shown in Fig. 11.1.7. This rapid scaling of 3D-flash technologies is possible since it is free from the lithography limitation mentioned above. This paper describes a 512Gbit 3b/cell flash fabricated with a 64-word-line-layer BiCS technology. In this work, we implemented three technologies: (1) four-block even-odd-combined row decoding to effectively address the increase of stacked layers; (2) unselected string pre-charge operation to improve endurance and reliability, and; (3) shielded BL current sensing to enhance read throughput. Figure 11.1.1 shows the die photo and the summary of key features.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
