基于层次综合的量子电路再优化

Xin-Chuan Wu, M. Davis, F. Chong, Costin Iancu
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引用次数: 8

摘要

量子计算的当前阶段处于噪声中等规模量子(NISQ)时代。在NISQ设备上,像cnos这样的双量子位门比单量子位门噪声大得多,因此必须尽量减少它们的计数。量子电路合成是将任意酉元分解成一系列量子门的过程,可以作为优化工具来生产更短的电路,以提高整体电路的保真度。然而,合成的解时间随着量子位的数量呈指数增长。因此,对于大量子位元规模的电路来说,合成是难以处理的。在本文中,我们提出了一个分层的,逐块优化框架,QGo,用于量子电路优化。我们的方法允许指数成本优化扩展到大型电路。QGo采用分区与合成相结合的方法:1)将电路划分为一系列独立的电路块;2)利用量子合成对每个区块进行重新生成和优化;3)通过将所有模块拼接在一起重新组合最终电路。我们在三种不同的情况下进行了分析并展示了保真度的改进:实际设备上的小尺寸电路,噪声模拟上的中等尺寸电路,分析模型上的大尺寸电路。我们的技术可以在现有优化后应用,以达到更高的电路保真度。使用一组NISQ基准测试,我们发现QGo可以将CNOT门的数量平均减少29.9%,与工业编译器优化(如it / ket)相比,可以减少高达50%。当在IBM Athens系统上执行时,较短的深度导致更高的电路保真度。我们还展示了我们的QGo技术的可扩展性,以优化60+量子比特的电路,我们的技术是第一次成功地在大型电路的编译工具链中使用和扩展合成的演示。总的来说,我们的方法对于直接集成到生产编译器工具链中以进一步提高电路保真度是健壮的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Reoptimization of Quantum Circuits via Hierarchical Synthesis
The current phase of quantum computing is in the Noisy Intermediate-Scale Quantum (NISQ) era. On NISQ devices, two-qubit gates such as CNOTs are much noisier than single-qubit gates, so it is essential to minimize their count. Quantum circuit synthesis is a process of decomposing an arbitrary unitary into a sequence of quantum gates, and can be used as an optimization tool to produce shorter circuits to improve overall circuit fidelity. However, the time-to-solution of synthesis grows exponentially with the number of qubits. As a result, synthesis is intractable for circuits on a large qubit scale. In this paper, we propose a hierarchical, block-by-block opti-mization framework, QGo, for quantum circuit optimization. Our approach allows an exponential cost optimization to scale to large circuits. QGo uses a combination of partitioning and synthesis: 1) partition the circuit into a sequence of independent circuit blocks; 2) re-generate and optimize each block using quantum synthesis; and 3) re-compose the final circuit by stitching all the blocks together. We perform our analysis and show the fidelity improvements in three different regimes: small-size circuits on real devices, medium-size circuits on noisy simulations, and large-size circuits on analytical models. Our technique can be applied after existing optimizations to achieve higher circuit fidelity. Using a set of NISQ benchmarks, we show that QGo can reduce the number of CNOT gates by 29.9% on average and up to 50% when compared with industrial compiler optimizations such as t|ket). When executed on the IBM Athens system, shorter depth leads to higher circuit fidelity. We also demonstrate the scalability of our QGo technique to optimize circuits of 60+ qubits, Our technique is the first demonstration of successfully employing and scaling synthesis in the compilation tool chain for large circuits. Overall, our approach is robust for direct incorporation in production compiler toolchains to further improve the circuit fidelity.
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