高性能CMOS静态逻辑电路设计

Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI:10.1109/MWSCAS.2001.986262

Ko-Chi Kuo, B. Carlson

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引用次数: 3

摘要

提出了一种采用新型电路技术实现的高性能CMOS静态逻辑电路。使用新的时钟方案和电路设计，对门输出进行了预处理，以最大限度地减少延迟。模拟的CLA电路表明，对于0.25 /spl mu/m的过程，平均功率延迟积比静态实现小1.62倍。

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High performance CMOS static logic circuit design

A high performance CMOS static logic implemented by a new circuit technique is presented. The gate outputs are preconditioned to minimize delay using a new clocking scheme and circuit design. The simulated CLA circuit shows that the average power-delay product is 1.62 times smaller than the static implementations for a 0.25 /spl mu/m process.

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Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)

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