用相关时钟降低1位CT δ - σ调制器的时钟抖动效应

2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2017-10-01 DOI:10.1109/EDSSC.2017.8126421

Yang Da-xiang, Li Debajit Basak, K. Pun

{"title":"用相关时钟降低1位CT δ - σ调制器的时钟抖动效应","authors":"Yang Da-xiang, Li Debajit Basak, K. Pun","doi":"10.1109/EDSSC.2017.8126421","DOIUrl":null,"url":null,"abstract":"A new technique to reduce the clock jitter effect on single-bit continuous-time delta-sigma modulators (CTDSM) is proposed. It utilizes a delay line to generate N highly correlated clock sources to reconstruct the feedback waveform. Theoretical analysis show that the jitter-induced random noise power is reduced by a factor of 1/N2. Simulation results confirming the analysis are reported.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"260 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Reduction of clock jitter effect in 1-bit CT delta-sigma modulators by correlated clocks\",\"authors\":\"Yang Da-xiang, Li Debajit Basak, K. Pun\",\"doi\":\"10.1109/EDSSC.2017.8126421\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new technique to reduce the clock jitter effect on single-bit continuous-time delta-sigma modulators (CTDSM) is proposed. It utilizes a delay line to generate N highly correlated clock sources to reconstruct the feedback waveform. Theoretical analysis show that the jitter-induced random noise power is reduced by a factor of 1/N2. Simulation results confirming the analysis are reported.\",\"PeriodicalId\":163598,\"journal\":{\"name\":\"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)\",\"volume\":\"260 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2017.8126421\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2017.8126421","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

提出了一种减小单比特连续时间δ - σ调制器时钟抖动的新方法。它利用延迟线产生N个高度相关的时钟源来重建反馈波形。理论分析表明，抖动引起的随机噪声功率降低了1/N2。仿真结果证实了分析的正确性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Reduction of clock jitter effect in 1-bit CT delta-sigma modulators by correlated clocks

A new technique to reduce the clock jitter effect on single-bit continuous-time delta-sigma modulators (CTDSM) is proposed. It utilizes a delay line to generate N highly correlated clock sources to reconstruct the feedback waveform. Theoretical analysis show that the jitter-induced random noise power is reduced by a factor of 1/N2. Simulation results confirming the analysis are reported.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)

自引率

0.00%

发文量