完全自同步1024位RSA密码引擎在40nm CMOS

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI:10.1109/ASSCC.2013.6691044

B. Devlin, M. Ikeda, Hiroshi Ueki, Kazuhiko Fukushima

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引用次数: 6

摘要

我们设计并测量了完全自同步的1024位RSA密码引擎，该引擎采用40nm CMOS制造。为了展示自同步、门级流水线架构的性能，我们实现了两种模块化幂运算算法，高到低(html)和蒙哥马利功率阶梯(MPL)。这两种实现采用相同的数据路径和804k晶体管，只有控制器不同，两个交错的1024b加密操作在1.1V标称电源下，html需要6.1ms到3.1ms, MPL需要6.0ms。

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Completely self-synchronous 1024-bit RSA crypt-engine in 40nm CMOS

We have designed and measured completely self-synchronous 1024-bit RSA crypt-engine, fabricated in 40nm CMOS. We have implemented two modular exponentiation algorithms, the high-to-low(HTL) and Montgomery power ladder(MPL) in order to show the performance of the self-synchronous, gate-level pipelined architectures. Both implementations employ identical data-paths and take 804k transistors, with only difference in controller, and two interleaved 1024b cryptographic operations take from 6.1ms to 3.1ms for HTL and 6.0ms for MPL, at nominal power supply of 1.1V.

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2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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