4.9 1ms高速视觉芯片，采用3d堆叠140GOPS柱平行pe进行时空图像处理

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI:10.1109/ISSCC.2017.7870271

Tomohiro Yamazaki, H. Katayama, S. Uehara, Atsushi Nose, M. Kobayashi, Sayaka Shida, Masaki Odahara, Kenichi Takamiya, Yasuaki Hisamatsu, S. Matsumoto, Leo Miyashita, Yoshihiro Watanabe, Takashi Izawa, Y. Muramatsu, M. Ishikawa

{"title":"4.9 1ms高速视觉芯片，采用3d堆叠140GOPS柱平行pe进行时空图像处理","authors":"Tomohiro Yamazaki, H. Katayama, S. Uehara, Atsushi Nose, M. Kobayashi, Sayaka Shida, Masaki Odahara, Kenichi Takamiya, Yasuaki Hisamatsu, S. Matsumoto, Leo Miyashita, Yoshihiro Watanabe, Takashi Izawa, Y. Muramatsu, M. Ishikawa","doi":"10.1109/ISSCC.2017.7870271","DOIUrl":null,"url":null,"abstract":"High-speed vision systems that combine high-frame-rate imaging and highly parallel signal processing enable instantaneous visual feedback to rapidly control machines over human-visual-recognition speeds. Such systems also enable a reduction in circuit scale by using a fast and simple algorithm optimized for high-frame-rate processing [1]. Previous studies on vision systems and chips [1–4] have yielded low imaging performance due to large matrix-based processing element (PE) parallelization [1–3], and low functionality of the limited-purpose column-parallel PE architecture [4], constraining vision-chip applications.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"53","resultStr":"{\"title\":\"4.9 A 1ms high-speed vision chip with 3D-stacked 140GOPS column-parallel PEs for spatio-temporal image processing\",\"authors\":\"Tomohiro Yamazaki, H. Katayama, S. Uehara, Atsushi Nose, M. Kobayashi, Sayaka Shida, Masaki Odahara, Kenichi Takamiya, Yasuaki Hisamatsu, S. Matsumoto, Leo Miyashita, Yoshihiro Watanabe, Takashi Izawa, Y. Muramatsu, M. Ishikawa\",\"doi\":\"10.1109/ISSCC.2017.7870271\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"High-speed vision systems that combine high-frame-rate imaging and highly parallel signal processing enable instantaneous visual feedback to rapidly control machines over human-visual-recognition speeds. Such systems also enable a reduction in circuit scale by using a fast and simple algorithm optimized for high-frame-rate processing [1]. Previous studies on vision systems and chips [1–4] have yielded low imaging performance due to large matrix-based processing element (PE) parallelization [1–3], and low functionality of the limited-purpose column-parallel PE architecture [4], constraining vision-chip applications.\",\"PeriodicalId\":269679,\"journal\":{\"name\":\"2017 IEEE International Solid-State Circuits Conference (ISSCC)\",\"volume\":\"171 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"53\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE International Solid-State Circuits Conference (ISSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2017.7870271\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2017.7870271","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 53

摘要

高速视觉系统结合了高帧率成像和高度并行的信号处理，使即时视觉反馈能够快速控制机器，超过人类视觉识别速度。这种系统还可以通过使用针对高帧率处理优化的快速简单算法来减小电路规模[1]。先前对视觉系统和芯片的研究[1-4]，由于基于矩阵的处理单元(PE)并行化程度高[1-3]，以及有限用途列并行PE架构的低功能[4]，导致成像性能较低，限制了视觉芯片的应用。

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4.9 A 1ms high-speed vision chip with 3D-stacked 140GOPS column-parallel PEs for spatio-temporal image processing

High-speed vision systems that combine high-frame-rate imaging and highly parallel signal processing enable instantaneous visual feedback to rapidly control machines over human-visual-recognition speeds. Such systems also enable a reduction in circuit scale by using a fast and simple algorithm optimized for high-frame-rate processing [1]. Previous studies on vision systems and chips [1–4] have yielded low imaging performance due to large matrix-based processing element (PE) parallelization [1–3], and low functionality of the limited-purpose column-parallel PE architecture [4], constraining vision-chip applications.

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2017 IEEE International Solid-State Circuits Conference (ISSCC)

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