一种空间变型OT-MACH滤波器的实现和性能评估,用于使用前红外传感器的安全检测应用

A. Gardezi, Ahmad Alkandri, P. Birch, T. Qureshi, R. Young, C. Chatwin
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引用次数: 1

摘要

一种空间变优权衡-最大平均相关高度(OT-MACH)滤波器专门针对前视红外(FLIR)传感器获取的图像设计,使用输入图像的最大功率谱密度(PSD)而不是白噪声协方差因子。内核可以根据其在输入帧中的位置进行局部修改,这使得滤波器能够根据背景热特征方差进行调整,并且还可以实现滤波器能级的规范化。使用不同的真实图像数据集和可疑威胁的3D模型来评估滤波器的检测能力,以便定义阈值参数。该参数基于相关输出的峰值与相关能(PCE)和峰值与旁瓣比(PSR),从而定义了预测真检测和假检测的标准。从FPGA和DSP芯片组的角度讨论了系统的硬件实现,并使用每秒数百万次乘法累积操作(MMAC)和成本创建了性能基准。在本文中,我们提出了一个安全检测应用的实现和性能评估,该应用使用具有不同数据集的空间变OT-MACH滤波器。此外,本文还为系统在FPGA和DSP芯片上的硬件实现建立了性能基准。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An implementation and performance evaluation of a space variant OT-MACH filter for a security detection application using FLIR sensor
A space variant Optimal Trade-off Maximum Average Correlation Height (OT-MACH) filter is designed specifically for images acquired from a forward looking infrared (FLIR) sensor, using the maximum of the power spectral density (PSD) of the input image instead of the white noise covariance factor. The kernel can be locally modified depending upon its position in the input frame, which enables adaptation of the filter dependant on background heat signature variances and also enables the normalization of the filter energy levels. The detection capabilities of the filter were evaluated using different data sets of real images and 3D models for a suspected threat in order to define a thresholding parameter. The parameter was based on peak to correlation energy (PCE) and peak to side lobe ratio (PSR) of the correlation output which led to the definition of a criterion for predicting true and false detections. The hardware implementation of the system has been discussed in terms of FPGA versus DSP chipsets and a performance benchmark has been created using millions of multiply-accumulate operations per second (MMAC) and the cost. In this paper we propose an implementation and performance evaluation of a security detection application which uses a space variant OT-MACH filter with different data sets. Also a performance benchmark has been created for the hardware implementation of the proposed system on popular FPGA and DSP chipsets.
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