通过在单个FPGA中使用8/7过采样的时序恢复实现168gb /s线率实时PAM接收器

2017 Optical Fiber Communications Conference and Exhibition (OFC) Pub Date : 2017-03-19 DOI:10.1364/OFC.2017.W2A.24

A. Josten, B. Baeuerle, M. Eppenberger, E. Dornbierer, D. Hillerkuss, J. Leuthold

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引用次数: 6

摘要

演示了一个以32gsa /s的速度工作于28gbd的实时接收器。信号处理在单个FPGA上完成。节省资源的8/7非整数过采样是通过频域的定时同步实现的。

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168 Gb/s line rate real-time PAM receiver enabled by timing recovery with 8/7 oversampling in a single FPGA

Demonstration of a real-time receiver working with 28 GBd at 32 GSa/s. The signal processing is done on a single FPGA. The resource-saving non-integer oversampling of 8/7 is enabled by a timing synchronization in the frequency domain.

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2017 Optical Fiber Communications Conference and Exhibition (OFC)

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