基于平方根进位选择加法器技术的MDCLCG硬件安全

M. Sushmitha, K. Jamal, M. Kiran, O. V. P. Kumar Manchalla, Ch Pratyusha Chowdari
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引用次数: 0

摘要

三操作数加法器利用各种密码算法,完成加法、乘法、求幂等模块化算术运算。在这里,使用伪随机位生成器算法进行加法运算。它以二进制格式执行,减少了面积,延迟,功率和提高了速度。在本加法器应用中,采用MDCLCG来提高硬件安全性和核心轻量化。与所有其他lcg和现有的PBRG技术相比,MDCLCG是更安全且极随机的PRBG方法。现有的MDCLCG可以处理增加的操作数大小,但它不能很好地处理三操作数加法器以提高性能。因此,将SRCSA集成到MDCLCG中可以获得比现有体系结构更好的结果。平方根进位保存加法器(SRCSA)是使用N-1加法器对所有N个偏积进行顺序相加的最简单技术之一。本研究旨在利用三操作数二进制加法器技术改善MDCLCG的硬件安全性。新颖的MDCLCG结构可以在Xilinx工具中执行32位,从而获得较好的仿真和合成效果。除了lcg、FIR和IIR滤波器、ALU处理器、基于随机的验证等之外,还使用该架构。这些加法器执行8位,16位,32位,64位和128位架构,然后使用Verilog-HDL实现,进一步的综合显示了比现有架构更小的面积,更低的功耗和更低的速度和更低的延迟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
MDCLCG with Square Root Carry Select Adder Technique for Hardware Security
Three-operand adder performs the modular arithmetic operations like addition, multiplication and exponentiation by utilizing various cryptography algorithms. Here, the pseudo-random bit generator algorithm is used to perform addition operation. It performs in binary format and reduces the area, delay, power and increases the speed. In this adder application purpose, the MDCLCG is used to increase the hardware security and light-weighted core. In comparison to all other LCGs and present PBRG techniques, MDCLCG is the more secure and extremely random PRBG approach. The existing MDCLCG can work on the increased operand size but it does not perform well with the three-operand adder to improve the performance. Hence, the SRCSA in integrated to the MDCLCG to obtain better result than existing architectures. Square-Root Carry Save Adder (SRCSA) is one of the simplest techniques used to sequentially add all N partial products by using N-1 adders. This research study intends to improve the implementation of MDCLCG with three-operand binary adder technique for hardware security. The novel MDCLCG architecture can execute 32-bits in Xilinx tool to obtain a better simulation and synthesis result. This architecture is used in addition to the LCGs, FIR and IIR filters, ALU processor, randomness-based verification, etc. These adders execute 8-bits, 16-bits, 32-bits, 64-bits and 128-bits architecture and it is then implemented by using Verilog-HDL and further the synthesis shows the report of less area, less power consumption and high speed with reduced delay than existing architectures.
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