{"title":"180nm工艺下低功耗10位2 ms /s连续逼近寄存器ADC的研究","authors":"Nam Anh Ha, Trang Hoang","doi":"10.1109/atc52653.2021.9598210","DOIUrl":null,"url":null,"abstract":"This paper presents Successive Approximation Register (SAR) ADC design in 180nm TSMC technology. The ADC can provide a high effective number of bits (ENOB), high speed and low power. At a 1.8-V supply and 2 MS/s, our design achieves an SNDR of 59.5 dB, ENOB 9.59 bit and consumes 1.17 mW, resulting in a figure of merit (FOM) of 759 fJ/conversion-step. To attain the mentioned results, the SAR architecture is proposed to use SAR ADC fully differential with S/H circuit, Capacitive DAC, Dynamic latch comparator, SAR Logic.","PeriodicalId":196900,"journal":{"name":"2021 International Conference on Advanced Technologies for Communications (ATC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A study of 10-bit 2-MS/s Successive Approximation Register ADC with low power in 180nm technology\",\"authors\":\"Nam Anh Ha, Trang Hoang\",\"doi\":\"10.1109/atc52653.2021.9598210\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents Successive Approximation Register (SAR) ADC design in 180nm TSMC technology. The ADC can provide a high effective number of bits (ENOB), high speed and low power. At a 1.8-V supply and 2 MS/s, our design achieves an SNDR of 59.5 dB, ENOB 9.59 bit and consumes 1.17 mW, resulting in a figure of merit (FOM) of 759 fJ/conversion-step. To attain the mentioned results, the SAR architecture is proposed to use SAR ADC fully differential with S/H circuit, Capacitive DAC, Dynamic latch comparator, SAR Logic.\",\"PeriodicalId\":196900,\"journal\":{\"name\":\"2021 International Conference on Advanced Technologies for Communications (ATC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-10-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 International Conference on Advanced Technologies for Communications (ATC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/atc52653.2021.9598210\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 International Conference on Advanced Technologies for Communications (ATC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/atc52653.2021.9598210","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A study of 10-bit 2-MS/s Successive Approximation Register ADC with low power in 180nm technology
This paper presents Successive Approximation Register (SAR) ADC design in 180nm TSMC technology. The ADC can provide a high effective number of bits (ENOB), high speed and low power. At a 1.8-V supply and 2 MS/s, our design achieves an SNDR of 59.5 dB, ENOB 9.59 bit and consumes 1.17 mW, resulting in a figure of merit (FOM) of 759 fJ/conversion-step. To attain the mentioned results, the SAR architecture is proposed to use SAR ADC fully differential with S/H circuit, Capacitive DAC, Dynamic latch comparator, SAR Logic.
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