Advanced technology mapping for standard-cell generators

In this paper, a new algorithm for technology mapping aiming at standard-cell generators is proposed. The proposed method has features that explore several AND/OR circuit decompositions by using an n-ary tree representation of the circuit. In the covering step, the cell that leads to the smaller depth increase is chosen. Depth calculation is not limited to the subject tree and takes into account all previously mapped trees representing sub-expressions used as inputs. Experimental results show gains in circuit depth measured by the number of gates in series, as well as in area measured by transistor count when compared to SIS mapping approach using the same libraries. The gain in circuit depth translates to better timing as verified by SPICE simulations.