数字辅助低功耗流水线模数转换器

2015 IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW) Pub Date : 2015-05-07 DOI:10.1109/EICONRUSNW.2015.7102273

I. Piatak, D. Morozov, M. Pilipko

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摘要

本文讨论了低功耗CMOS流水线模数转换器(adc)结构的主要方面。定义了流水线ADC的1.5位冗余级的主要要求。考虑了结合功率降低机制的流水线ADC的数字和模拟纠错机制的例子。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Digitally assisted low-power pipelined analog-to-digital converters

In this paper the main aspects in construction of the low-power CMOS pipelined analog-to-digital converters (ADCs) are discussed. The main requirements for a 1.5 bit redundant stage of the pipeline ADC are defined. Examples of the digital and the analog error correction mechanisms for the pipelined ADC in conjunction with the power reduction mechanisms are considered.

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来源期刊

2015 IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW)

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