{"title":"用于GSM/GPRS/EDGE的90 nm CMOS接收器前端","authors":"S. Fang, F. Dulger, A. Bellaouar, M. Frechette","doi":"10.1109/RWS.2006.1615109","DOIUrl":null,"url":null,"abstract":"A GSM/GPRS/EDGE receiver front-end realized in 90 nm CMOS technology is presented. With a low power of 46 mW, it achieved 31.5 dB gain, 2.1 dB integrated noise figure, 5 dB of noise figure under blocking condition and -9.5 dBm of inband IIP3. The measured LO leakage at the LNA input is 125 dBm. Total active area occupies 1.4 mm/sup 2/.","PeriodicalId":244560,"journal":{"name":"2006 IEEE Radio and Wireless Symposium","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 90 nm CMOS receiver front-end for GSM/GPRS/EDGE\",\"authors\":\"S. Fang, F. Dulger, A. Bellaouar, M. Frechette\",\"doi\":\"10.1109/RWS.2006.1615109\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A GSM/GPRS/EDGE receiver front-end realized in 90 nm CMOS technology is presented. With a low power of 46 mW, it achieved 31.5 dB gain, 2.1 dB integrated noise figure, 5 dB of noise figure under blocking condition and -9.5 dBm of inband IIP3. The measured LO leakage at the LNA input is 125 dBm. Total active area occupies 1.4 mm/sup 2/.\",\"PeriodicalId\":244560,\"journal\":{\"name\":\"2006 IEEE Radio and Wireless Symposium\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-04-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Radio and Wireless Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RWS.2006.1615109\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Radio and Wireless Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RWS.2006.1615109","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A GSM/GPRS/EDGE receiver front-end realized in 90 nm CMOS technology is presented. With a low power of 46 mW, it achieved 31.5 dB gain, 2.1 dB integrated noise figure, 5 dB of noise figure under blocking condition and -9.5 dBm of inband IIP3. The measured LO leakage at the LNA input is 125 dBm. Total active area occupies 1.4 mm/sup 2/.
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