Optimizing Fin Aspect Ratio of Junctionless Bulk FinFET for Application in Analog/RF Circuit

MOSFET devices with multiple gates are well appropriate for low-voltage operation because of its superior performance against Short Channel Effects (SCEs) and better gate controllability. FinFET is considered as one of the promising device. However, Fin geometry has a big impact on its performance. In this paper, an analysis on the effect of Fin structure parameter like Fin aspect ratio (Fin height/Fin width) on the Analog/RF performance of the Junctionless FinFET is presented for its SoC application. Different important output parameters such as OFF current $(\mathrm{I}_{\mathrm{O}\mathrm{F}\mathrm{F}})$ ON current $(\mathrm{I}_{\mathrm{O}\mathrm{N}}),\mathrm{I}_{\mathrm{O}\mathrm{N}}{/}\mathrm{I}_{\mathrm{O}\mathrm{F}\mathrm{F}}$ current ratio, Transconductance $(\mathrm{g}_{\mathrm{m}})$ Transconductance Generation Factor $(\mathrm{g}_{\mathrm{m}}/\mathrm{I}_{\mathrm{d}\mathrm{s}})$ Cut-off Frequency $(\mathrm{f}_{\mathrm{T}})$ and Maximum frequency of oscillation $(\mathrm{f}_{\max})$ have been analyzed using TCAD device simulator. From the analysis it is established that the device presented in this work shows better $\mathrm{I}_{\mathrm{O}\mathrm{N}}, \mathrm{I}_{\mathrm{O}\mathrm{F}\mathrm{F}}, \ \ \mathrm{I}_{\mathrm{O}\mathrm{N}}/\mathrm{I}_{\mathrm{O}\mathrm{F}\mathrm{F}}$ Transconductance, and Transconductance generation factor if Fin structure having higher aspect ratio is used. However, slight decrement in $\mathrm{f}_{\mathrm{T}}$ and fmaxare noticed when the Fin aspect ratio is high. Findings of this work will be helpful for design of devices for its specific applications.