3-D semiconductor’s: More from moore

Over the past 40 years, the semiconductor industry has exponentially driven cost per function down following the oft stated Moores Law. It is becoming increasingly difficult to scale as we move into the 32 nm and beyond process nodes due both to physics and economics. A lower cost alternative method of scaling is becoming more available in the form of vertical chip integration. Many manufacturers now offer a range of package level integration solutions from traditional planar approaches to commonly used die stacking and recently introduced die level 3-D integration. With the introduction of 3-D integration, designers and system integrators can now consider physical design optimizations which include functional stacking, through silicon interconnect to reduce power and signal latency, and optimized manufacturing cost. To enable design teams to take advantage of the benefits available with this technology, new capabilities must be developed to support the design and implementation process. This support must start at the architectural level where issues of robustness, reliability, testability and power must be thoroughly studied. Support must continue through to manufacturing, packaging, and final test development. In this presentation we will explore how existing design technology and methods can be practically evolved to support the powerful scaling capabilities inherent in 3-D integration technology. Specifically we will cover Architectural design space exploration, functional partitioning, physical planning, and timing/SI/thermal/yield analysis for 3-D structures.