Optimal systolic block size for low power high speed digital allpass filters based on the 3-port adaptor

Allpass digital filters are major building blocks in many digital filter architectures. In this paper an optimal pipelined architecture for a 2nd order allpass section based on 3-port adaptor is proposed. Optimal pipelining improves the filter's overall performance in term of power-delay-area by 4.8 times using 1 /spl mu/m CMOS standard cell design and by 10 times using custom cells. Given the same clock speed and without the use of supply voltage scaling, the architecture consumes 58% less power than the non-pipelined equivalent using custom cell implementation and by 50% using standard cells. With a maximum throughput of 277 MHz, the adaptor's power consumption is 5.44 mW/MHz, representing a 64% improvement in power efficiency relative to the non-pipelined standard cell adaptor.