A. Fujihara, E. Mizuki, H. Miyamoto, Y. Makino, K. Yamanoguchi, N. Samoto
{"title":"采用具有AlAs/InAs超晶格层的InP异质结fet的高性能60 ghz共面MMIC LNA","authors":"A. Fujihara, E. Mizuki, H. Miyamoto, Y. Makino, K. Yamanoguchi, N. Samoto","doi":"10.1109/MWSYM.2000.860876","DOIUrl":null,"url":null,"abstract":"We describe a 60-GHz coplanar MMIC low-noise amplifier (LNA) using 0.1 /spl mu/m-gate-length InP heterojunction FETs (HJFETs). An optimum gate width of 80 /spl mu/m was determined for the first stage FET by using a small signal model including accurate scaling of the gate resistance. On-wafer noise measurements demonstrated a noise figure of 2.2 dB and a gain of 22.8 dB at 60 GHz.","PeriodicalId":305585,"journal":{"name":"2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"High performance 60-GHz coplanar MMIC LNA using InP heterojunction FETs with AlAs/InAs superlattice layer\",\"authors\":\"A. Fujihara, E. Mizuki, H. Miyamoto, Y. Makino, K. Yamanoguchi, N. Samoto\",\"doi\":\"10.1109/MWSYM.2000.860876\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We describe a 60-GHz coplanar MMIC low-noise amplifier (LNA) using 0.1 /spl mu/m-gate-length InP heterojunction FETs (HJFETs). An optimum gate width of 80 /spl mu/m was determined for the first stage FET by using a small signal model including accurate scaling of the gate resistance. On-wafer noise measurements demonstrated a noise figure of 2.2 dB and a gain of 22.8 dB at 60 GHz.\",\"PeriodicalId\":305585,\"journal\":{\"name\":\"2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096)\",\"volume\":\"124 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSYM.2000.860876\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSYM.2000.860876","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High performance 60-GHz coplanar MMIC LNA using InP heterojunction FETs with AlAs/InAs superlattice layer
We describe a 60-GHz coplanar MMIC low-noise amplifier (LNA) using 0.1 /spl mu/m-gate-length InP heterojunction FETs (HJFETs). An optimum gate width of 80 /spl mu/m was determined for the first stage FET by using a small signal model including accurate scaling of the gate resistance. On-wafer noise measurements demonstrated a noise figure of 2.2 dB and a gain of 22.8 dB at 60 GHz.