一个5Gbit/s CMOS时钟和数据恢复电路

2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI:10.1109/EDSSC.2005.1635295

Tan Kok-Siang, M.S. Sulainian, Tan Soon-Hwei, M. Reaz, F. Mohd-Yasin

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引用次数: 2

摘要

本文提出了一种半速率5Gb/s时钟和数据恢复电路。数据的重定时是由线性PD完成的，它几乎没有为感兴趣的频带提供系统偏移。该电路采用0.18 μm CMOS工艺设计，有效面积为0.2 x 0.32 mm2。CDR的RMS抖动为±1.2 ps，峰间抖动为5ps。1.8 v电源的功耗为97mW。

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A 5Gbit/s CMOS Clock and Data Recovery Circuit

This paper presents a half-rate 5Gb/s clock and data recovery circuit. Retiming of data is done by the linear PD that provides practically no systematic offset for the frequency band of interest. The circuit was designed in a 0.18-μm CMOS process and occupies an active area of 0.2 x 0.32 mm2. The CDR exhibits an RMS jitter of ±1.2 ps and a peak-to-peak jitter of 5ps. The power dissipation is 97mW from a 1.8-V supply.

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2005 IEEE Conference on Electron Devices and Solid-State Circuits

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