SI/EMC和可靠性问题如何在嵌入式电子系统中相互作用?

K. Weide-Zaage, A. Moujbani, G. Duchamp, T. Dubois, F. Verdier, H. Frémont
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引用次数: 0

摘要

集成电路的设计过程是以技术可行性为指导,以达到最小的结构尺寸。此外,电路的可靠性和寿命等质量标准也会影响布局。晶体管的密度增加,供电电压和噪声裕度也增加。在这种情况下,必须考虑到信号完整性以及IC互连的电磁行为,印刷电路板上的走线,封装的连接。特别是在三维集成和恶劣环境条件下,需要对电磁场进行研究。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
How SI/EMC and reliability issues could interact together in embedded electronic systems?
The design process of integrated circuits is based on guidelines by the technological feasibility to achieve minimum structural size. Furthermore quality criteria like reliability and lifetime of the circuit influence the layout. The density of transistors increases and the supplied voltages as well as the noise margins also increase. In this frame the signal integrity as well as the electromagnetic behavior of IC interconnects, the traces in the printed circuit board, the connections of packages, have to be taken into account. Especially in 3-D integration and under harsh environment conditions the electromagnetic field has to be investigated.
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