{"title":"基于总线的IP复用验证平台","authors":"Wenfa Zhan, Rui Wang, Duoli Zhang, Bing Lu","doi":"10.1109/EDSSC.2005.1635386","DOIUrl":null,"url":null,"abstract":"As the VLSI design scale shrinks, traditional verification methods can not satisfy the verification request, because they do not provide enough ability to check the function correctness and can not ensure the product quality. Verification has become the bottleneck of integrated circuit design. A method of bus based verification platform is presented and the reusable efficience can be improved 80% at least. The focus is to increase the productivity of the verification engineer by providing a framework to reuse verification unit.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Bus-based IP Reusable Verification Platform\",\"authors\":\"Wenfa Zhan, Rui Wang, Duoli Zhang, Bing Lu\",\"doi\":\"10.1109/EDSSC.2005.1635386\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As the VLSI design scale shrinks, traditional verification methods can not satisfy the verification request, because they do not provide enough ability to check the function correctness and can not ensure the product quality. Verification has become the bottleneck of integrated circuit design. A method of bus based verification platform is presented and the reusable efficience can be improved 80% at least. The focus is to increase the productivity of the verification engineer by providing a framework to reuse verification unit.\",\"PeriodicalId\":429314,\"journal\":{\"name\":\"2005 IEEE Conference on Electron Devices and Solid-State Circuits\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 IEEE Conference on Electron Devices and Solid-State Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2005.1635386\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2005.1635386","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
As the VLSI design scale shrinks, traditional verification methods can not satisfy the verification request, because they do not provide enough ability to check the function correctness and can not ensure the product quality. Verification has become the bottleneck of integrated circuit design. A method of bus based verification platform is presented and the reusable efficience can be improved 80% at least. The focus is to increase the productivity of the verification engineer by providing a framework to reuse verification unit.
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