{"title":"智能像素在数字图像半色调中的应用","authors":"A. Sayles, B. Shoop","doi":"10.1109/ACSSC.1996.600969","DOIUrl":null,"url":null,"abstract":"An innovative circuit for digital image halftoning applications has been implemented in several different hybrid fabrication processes. The circuits have been demonstrated to be compatible with several approaches to smart pixels and offer a wide range of options for realizing optical inputs and outputs. The 0.8 micron n-well CMOS process at MOSIS has been used in conjunction with SEED technology to implement a digital image halftoning algorithm that offers the potential for higher quality binary images. Similar algorithms have also been implemented using combined CMOS and liquid crystal on silicon processes as well as the Vitesse H-GaAs III foundry process.","PeriodicalId":270729,"journal":{"name":"Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Application of smart pixels to digital image halftoning\",\"authors\":\"A. Sayles, B. Shoop\",\"doi\":\"10.1109/ACSSC.1996.600969\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An innovative circuit for digital image halftoning applications has been implemented in several different hybrid fabrication processes. The circuits have been demonstrated to be compatible with several approaches to smart pixels and offer a wide range of options for realizing optical inputs and outputs. The 0.8 micron n-well CMOS process at MOSIS has been used in conjunction with SEED technology to implement a digital image halftoning algorithm that offers the potential for higher quality binary images. Similar algorithms have also been implemented using combined CMOS and liquid crystal on silicon processes as well as the Vitesse H-GaAs III foundry process.\",\"PeriodicalId\":270729,\"journal\":{\"name\":\"Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ACSSC.1996.600969\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACSSC.1996.600969","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Application of smart pixels to digital image halftoning
An innovative circuit for digital image halftoning applications has been implemented in several different hybrid fabrication processes. The circuits have been demonstrated to be compatible with several approaches to smart pixels and offer a wide range of options for realizing optical inputs and outputs. The 0.8 micron n-well CMOS process at MOSIS has been used in conjunction with SEED technology to implement a digital image halftoning algorithm that offers the potential for higher quality binary images. Similar algorithms have also been implemented using combined CMOS and liquid crystal on silicon processes as well as the Vitesse H-GaAs III foundry process.