{"title":"基于FPGA的心脏阻塞检测图像处理算法的设计与实现","authors":"Shrinivas B Mudigoudar, A. Rasheed","doi":"10.1109/INDICON.2016.7839159","DOIUrl":null,"url":null,"abstract":"Nowadays, major health issues are concerned with heart problems say, heart attack. The main cause for heart attack is plaque. The Cardiac Plaque is waxy substance buildup inside the coronary arteries. Plaque results blockages inside the coronary arteries. The cardiac angiogram or cardiac catheterization is an approach used for the diagnosis of coronary blockages. It is an expensive and invasive approach to detect cardiac blockages. So, the angiogram is a conventional approach to diagnose cardiac blockages. In this paper, cardiac blockages are detected by means of Canny edge detector and Watershed image processing algorithms implemented on FPGA (Hardware implementation). The proposed design consumes power of 118 mW and maximum operating frequency is 338.295 MHz and minimum period is 2.956 ns.","PeriodicalId":283953,"journal":{"name":"2016 IEEE Annual India Conference (INDICON)","volume":"218 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Design and implementation of image processing algorithms for cardiac blockage detection on FPGA\",\"authors\":\"Shrinivas B Mudigoudar, A. Rasheed\",\"doi\":\"10.1109/INDICON.2016.7839159\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Nowadays, major health issues are concerned with heart problems say, heart attack. The main cause for heart attack is plaque. The Cardiac Plaque is waxy substance buildup inside the coronary arteries. Plaque results blockages inside the coronary arteries. The cardiac angiogram or cardiac catheterization is an approach used for the diagnosis of coronary blockages. It is an expensive and invasive approach to detect cardiac blockages. So, the angiogram is a conventional approach to diagnose cardiac blockages. In this paper, cardiac blockages are detected by means of Canny edge detector and Watershed image processing algorithms implemented on FPGA (Hardware implementation). The proposed design consumes power of 118 mW and maximum operating frequency is 338.295 MHz and minimum period is 2.956 ns.\",\"PeriodicalId\":283953,\"journal\":{\"name\":\"2016 IEEE Annual India Conference (INDICON)\",\"volume\":\"218 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Annual India Conference (INDICON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/INDICON.2016.7839159\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Annual India Conference (INDICON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INDICON.2016.7839159","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and implementation of image processing algorithms for cardiac blockage detection on FPGA
Nowadays, major health issues are concerned with heart problems say, heart attack. The main cause for heart attack is plaque. The Cardiac Plaque is waxy substance buildup inside the coronary arteries. Plaque results blockages inside the coronary arteries. The cardiac angiogram or cardiac catheterization is an approach used for the diagnosis of coronary blockages. It is an expensive and invasive approach to detect cardiac blockages. So, the angiogram is a conventional approach to diagnose cardiac blockages. In this paper, cardiac blockages are detected by means of Canny edge detector and Watershed image processing algorithms implemented on FPGA (Hardware implementation). The proposed design consumes power of 118 mW and maximum operating frequency is 338.295 MHz and minimum period is 2.956 ns.