{"title":"LDPC解码器中用于交错的多值双工异步数据传输方案","authors":"N. Onizawa, A. Mochizuki, T. Hanyu","doi":"10.1109/ISMVL.2005.29","DOIUrl":null,"url":null,"abstract":"A novel duplex asynchronous data-transfer scheme based on multiple-valued encoding is proposed for interleaving in low-density parity-check (LDPC) decoders, where high-throughput interleavers between variable and check nodes without clock-distribution problems are highly advantageous. Since control signals and data from mutual nodes are multiplexed using a multi-level dual-rail codeword, the number of communication steps can be greatly reduced, which results in high-speed communication without any additional wires. The hardware is simply implemented by utilizing a multiple-valued current-mode circuit because all the information can be superposed on the same line. The advantages of the proposed asynchronous data-transfer scheme are discussed in comparison with corresponding synchronous and conventional asynchronous schemes.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Multiple-valued duplex asynchronous data transfer scheme for interleaving in LDPC decoders\",\"authors\":\"N. Onizawa, A. Mochizuki, T. Hanyu\",\"doi\":\"10.1109/ISMVL.2005.29\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel duplex asynchronous data-transfer scheme based on multiple-valued encoding is proposed for interleaving in low-density parity-check (LDPC) decoders, where high-throughput interleavers between variable and check nodes without clock-distribution problems are highly advantageous. Since control signals and data from mutual nodes are multiplexed using a multi-level dual-rail codeword, the number of communication steps can be greatly reduced, which results in high-speed communication without any additional wires. The hardware is simply implemented by utilizing a multiple-valued current-mode circuit because all the information can be superposed on the same line. The advantages of the proposed asynchronous data-transfer scheme are discussed in comparison with corresponding synchronous and conventional asynchronous schemes.\",\"PeriodicalId\":340578,\"journal\":{\"name\":\"35th International Symposium on Multiple-Valued Logic (ISMVL'05)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-05-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"35th International Symposium on Multiple-Valued Logic (ISMVL'05)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.2005.29\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2005.29","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Multiple-valued duplex asynchronous data transfer scheme for interleaving in LDPC decoders
A novel duplex asynchronous data-transfer scheme based on multiple-valued encoding is proposed for interleaving in low-density parity-check (LDPC) decoders, where high-throughput interleavers between variable and check nodes without clock-distribution problems are highly advantageous. Since control signals and data from mutual nodes are multiplexed using a multi-level dual-rail codeword, the number of communication steps can be greatly reduced, which results in high-speed communication without any additional wires. The hardware is simply implemented by utilizing a multiple-valued current-mode circuit because all the information can be superposed on the same line. The advantages of the proposed asynchronous data-transfer scheme are discussed in comparison with corresponding synchronous and conventional asynchronous schemes.