基于多核网络处理器的分组缓存路由器的快速路径性能研究

2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems Pub Date : 2011-10-03 DOI:10.1109/ANCS.2011.22

Shu Yamamoto, A. Nakao

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引用次数: 2

摘要

报文缓存路由器实现报文级冗余数据消除功能，可以有效减少P2P集群流量穿越ISP域间链路。报文缓存路由器部署在ISP网络中，对报文处理性能有很高的要求。本文采用快路径/慢路径应用结构，利用多核网络处理器实现了一个数据包缓存路由器，并对其性能进行了评估。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Fast Path Performance of Packet Cache Router Using Multi-core Network Processor

The packet cache router enabling the packet-level redundant data elimination is effective to reduce the P2P swarm traffic traversing ISP inter-domain links. To deploy the packet cache router in the ISP networks, the high performance packet processing is required. In this paper, we implement a packet cache router by a multi-core network processor using fast path/slow path application structure and evaluate its performance.

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来源期刊

2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems

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