{"title":"一种用于MPU内存保护单元的内存分配方法","authors":"Xin Wang, Zhiqiang Wang, Qilong Hu, Lin Fan, Ling Yi, Jingben Xu","doi":"10.1109/ICCECT57938.2023.10141446","DOIUrl":null,"url":null,"abstract":"At present, the Memory Protection Unit (MPU) of Cortex-M series processors needs to align the address with the rule of 2n when protecting the memory, but this method will cause memory waste in multi-task memory allocation. Therefore, this paper proposes a method that uses multiple MPU protected regions to concatenate and superimpose to protect a region simultaneously, which effectively reduces the memory waste caused by alignment. The experimental results show that, compared with using a single MPU protected region, using four regions for concatenation and superposition can reduce the memory waste by 63%, and effectively improve the memory utilization.","PeriodicalId":314504,"journal":{"name":"2023 IEEE International Conference on Control, Electronics and Computer Technology (ICCECT)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A memory allocation method for MPU memory protection unit\",\"authors\":\"Xin Wang, Zhiqiang Wang, Qilong Hu, Lin Fan, Ling Yi, Jingben Xu\",\"doi\":\"10.1109/ICCECT57938.2023.10141446\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"At present, the Memory Protection Unit (MPU) of Cortex-M series processors needs to align the address with the rule of 2n when protecting the memory, but this method will cause memory waste in multi-task memory allocation. Therefore, this paper proposes a method that uses multiple MPU protected regions to concatenate and superimpose to protect a region simultaneously, which effectively reduces the memory waste caused by alignment. The experimental results show that, compared with using a single MPU protected region, using four regions for concatenation and superposition can reduce the memory waste by 63%, and effectively improve the memory utilization.\",\"PeriodicalId\":314504,\"journal\":{\"name\":\"2023 IEEE International Conference on Control, Electronics and Computer Technology (ICCECT)\",\"volume\":\"114 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-04-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 IEEE International Conference on Control, Electronics and Computer Technology (ICCECT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCECT57938.2023.10141446\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE International Conference on Control, Electronics and Computer Technology (ICCECT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCECT57938.2023.10141446","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A memory allocation method for MPU memory protection unit
At present, the Memory Protection Unit (MPU) of Cortex-M series processors needs to align the address with the rule of 2n when protecting the memory, but this method will cause memory waste in multi-task memory allocation. Therefore, this paper proposes a method that uses multiple MPU protected regions to concatenate and superimpose to protect a region simultaneously, which effectively reduces the memory waste caused by alignment. The experimental results show that, compared with using a single MPU protected region, using four regions for concatenation and superposition can reduce the memory waste by 63%, and effectively improve the memory utilization.