Fault Detection and Localization for Network-on-Chips in Mixed-Criticality Systems

The increasing trend towards mixed-critical systems, in which applications with different levels of criticality coexist and interact on the same platform, calls for fault-tolerant hardware platforms. On the other hand, due to the demanded performance in such systems, network-on-chips are employed to interconnect several computation resources. Consequently, the detection and localization of faults in the communication and computation resources becomes a challenge, if a high number of shared resources (e.g., routers, physical links) are used. This paper proposes a new hardware architecture for run-time fault detection and localization in mixed-criticality networks-on-chips. The proposed architecture detects the transient and permanent faults in the network and distinguishes between faults of different resources. The fault detection and localization mechanisms have been evaluated using Gem5 simulation and example scenarios.