Y. Nara, N. Mise, M. Kadoshima, T. Morooka, S. Kamiyama, T. Matsuki, M. Sato, T. Ono, T. Aoyama, T. Eimori, Y. Ohji
{"title":"用于先进CMOS技术的栅极优先高k/金属栅极堆栈","authors":"Y. Nara, N. Mise, M. Kadoshima, T. Morooka, S. Kamiyama, T. Matsuki, M. Sato, T. Ono, T. Aoyama, T. Eimori, Y. Ohji","doi":"10.1109/ICSICT.2008.4734777","DOIUrl":null,"url":null,"abstract":"Practical and manufacturable solutions for metal gate/dual high-k CMOS integration are presented. In order to overcome the difficulties of threshold voltage control of metal gate/high-k gate stack especially for gate-first integration, several material designs have been proposed so far. These include different metal gate materials and different high-k materials which are separately used in nMOS and pMOS transistors. These approaches sometimes bring about complicated CMOS integration scheme. In this paper, therefore, we will give simple metal gate/dual high-k CMOS fabrication processes with low threshold voltages which are suitable for scaled CMOS device manufacturing.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"110 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Gate-first high-k/metal gate stack for advanced CMOS technology\",\"authors\":\"Y. Nara, N. Mise, M. Kadoshima, T. Morooka, S. Kamiyama, T. Matsuki, M. Sato, T. Ono, T. Aoyama, T. Eimori, Y. Ohji\",\"doi\":\"10.1109/ICSICT.2008.4734777\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Practical and manufacturable solutions for metal gate/dual high-k CMOS integration are presented. In order to overcome the difficulties of threshold voltage control of metal gate/high-k gate stack especially for gate-first integration, several material designs have been proposed so far. These include different metal gate materials and different high-k materials which are separately used in nMOS and pMOS transistors. These approaches sometimes bring about complicated CMOS integration scheme. In this paper, therefore, we will give simple metal gate/dual high-k CMOS fabrication processes with low threshold voltages which are suitable for scaled CMOS device manufacturing.\",\"PeriodicalId\":436457,\"journal\":{\"name\":\"2008 9th International Conference on Solid-State and Integrated-Circuit Technology\",\"volume\":\"110 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 9th International Conference on Solid-State and Integrated-Circuit Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.2008.4734777\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.2008.4734777","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Gate-first high-k/metal gate stack for advanced CMOS technology
Practical and manufacturable solutions for metal gate/dual high-k CMOS integration are presented. In order to overcome the difficulties of threshold voltage control of metal gate/high-k gate stack especially for gate-first integration, several material designs have been proposed so far. These include different metal gate materials and different high-k materials which are separately used in nMOS and pMOS transistors. These approaches sometimes bring about complicated CMOS integration scheme. In this paper, therefore, we will give simple metal gate/dual high-k CMOS fabrication processes with low threshold voltages which are suitable for scaled CMOS device manufacturing.