{"title":"soc中高层次能量和性能评估的一般方法","authors":"S. Penolazzi, A. Hemani, Luca Bolognino","doi":"10.1109/VLSI.Design.2009.25","DOIUrl":null,"url":null,"abstract":"We present a high-level methodology for efficient and accurate estimation of energy and performance in SoCs at Functional Untimed Level. We then validate the proposed method against gate level for accuracy and against TLM-PV for speed. We show that the method is within 15 % of gate-level accuracy and in average 28x faster than TLM-PV, for the benchmark applications selected.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"94 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A General Approach to High-Level Energy and Performance Estimation in SoCs\",\"authors\":\"S. Penolazzi, A. Hemani, Luca Bolognino\",\"doi\":\"10.1109/VLSI.Design.2009.25\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a high-level methodology for efficient and accurate estimation of energy and performance in SoCs at Functional Untimed Level. We then validate the proposed method against gate level for accuracy and against TLM-PV for speed. We show that the method is within 15 % of gate-level accuracy and in average 28x faster than TLM-PV, for the benchmark applications selected.\",\"PeriodicalId\":267121,\"journal\":{\"name\":\"2009 22nd International Conference on VLSI Design\",\"volume\":\"94 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-01-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 22nd International Conference on VLSI Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI.Design.2009.25\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 22nd International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI.Design.2009.25","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A General Approach to High-Level Energy and Performance Estimation in SoCs
We present a high-level methodology for efficient and accurate estimation of energy and performance in SoCs at Functional Untimed Level. We then validate the proposed method against gate level for accuracy and against TLM-PV for speed. We show that the method is within 15 % of gate-level accuracy and in average 28x faster than TLM-PV, for the benchmark applications selected.