基于pMOS的经典低降差调节器的时域分析与建模

2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2021-12-01 DOI:10.1109/iSES52644.2021.00085

Antaryami Panigrahi, Gaurav Jyoti Dutta, Swarnav Bora, Kaushik Roy Baruah, Mukul Paul

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引用次数: 0

摘要

本文提出了一种以控制为中心的低降差(LDO)稳压器的分析与设计。通过信号流图(SFG)的发展，简化了调压回路频域相互依赖和调压性能参数的设计复杂性。在Matlab/Simulink环境下开发了基于SFG的模型，并对其进行了测试，达到了期望的时域和频域规格。基于所建立的模型，给出了给定稳态精度和沉降的时域优化。

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Analysis and Modelling of pMOS based Classical Low Drop Out Regulators: A Time Domain Perspective

A control centric analysis and design of the low drop out (LDO) voltage regulator is presented in this work. The design complexity involving interdependence of regulating loop in frequency domain and the performance parameters for voltage regulator is simplified for intuition by the development of signal flow graph (SFG). A model based on the SFG is developed and tested in Matlab/Simulink environment for a desired time and frequency domain specification. Time domain optimisation for a given steady state accuracy and settling is formulated based on the developed model.

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2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)

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