超低热预算CMOS工艺,适用于65nm节点低运行功耗应用

F. Ootsuka, H. Ozaki, T. Sasaki, K. Yamashita, H. Takada, N. Izumi, Y. Nakagawa, M. Hayashi, K. Kiyono, M. Yasuhira, T. Arikado
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引用次数: 12

摘要

本文介绍了65纳米节点超浅结CMOS晶体管的制备工艺和性能。闪光灯退火提高了具有固相外延延伸结的pfet的可驱动性。与300mm /spl φ /晶圆上的传统尖峰RTA相比,扩展结的结漏增加小于1个数量级。在无光晕注入的35 nm栅极长度下,出色的Vth控制和在0.9 V电源下的高开关速度证明了65 nm节点LOP(低工作功率)应用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Ultra-low thermal budget CMOS process for 65nm-node low-operation-power applications
This paper describes the fabrication process and the performance of 65 nm-node CMOS transistors which have ultra-shallow junctions. Flash lamp annealing enhances the drivability of pFETs with a solid phase epitaxial extension junction. The increase in the junction leakage of the extension junction is less than 1 order of magnitude as compared with that for the conventional spike RTA on a 300 mm/spl phi/ wafer. Excellent Vth control at 35 nm gate length without halo implantation and a high switching speed at 0.9 V power supply are demonstrated for 65 nm-node LOP (low operation power) applications.
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