Multiport Register File Design for High-Performance Embedded Cores

As the application areas of embedded SoCs continue to expand, there is a need to adopt general-purpose cores with higher performance. One method of achieving higher performance in general-purpose processors is to use superscalar execution, which exploits instruction-level parallelism to achieve higher performance by simultaneously executing multiple instructions. As the number of parallel execution lanes of the processor increases, more ports are required in the internal memory structures, including a register file, to enable reading or writing multiple data in parallel. As the number of ports increases, the power consumption and area of the register file become larger, and the design becomes exceedingly complex. Therefore, an elaborate design space exploration of such register files is crucial for developing higher-performance cores. In this paper, we discuss the design of multiport register files, especially for 32-bit out-of-order superscalar processors, and investigate the design space through SPICE simulations.