{"title":"一个高性能渲染引擎的架构","authors":"H. Ackermann, C. Hornung","doi":"10.2312/EGGH/EGGH91/157-174","DOIUrl":null,"url":null,"abstract":"We present an architecture for a high-performance programmable rendering engine. This chip or chip-set will be able to deliver one Gouraud-shaded, z-buffered, texturemodulated and alpha-blended pixel every clock cycle. Focus of the paper is the derivation of the architecture of the pixel processing block from the applied algorithms.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"233 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An Architecture for a High Performance Rendering Engine\",\"authors\":\"H. Ackermann, C. Hornung\",\"doi\":\"10.2312/EGGH/EGGH91/157-174\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present an architecture for a high-performance programmable rendering engine. This chip or chip-set will be able to deliver one Gouraud-shaded, z-buffered, texturemodulated and alpha-blended pixel every clock cycle. Focus of the paper is the derivation of the architecture of the pixel processing block from the applied algorithms.\",\"PeriodicalId\":206166,\"journal\":{\"name\":\"Advances in Computer Graphics Hardware\",\"volume\":\"233 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Advances in Computer Graphics Hardware\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.2312/EGGH/EGGH91/157-174\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Advances in Computer Graphics Hardware","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.2312/EGGH/EGGH91/157-174","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Architecture for a High Performance Rendering Engine
We present an architecture for a high-performance programmable rendering engine. This chip or chip-set will be able to deliver one Gouraud-shaded, z-buffered, texturemodulated and alpha-blended pixel every clock cycle. Focus of the paper is the derivation of the architecture of the pixel processing block from the applied algorithms.
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