K. Yoshioka, A. Shikata, Ryota Sekimoto, T. Kuroda, H. Ishikuro
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引用次数: 1
摘要
提出了一种超低电压、高速度、低功耗的2位/步异步SAR ADC。提出了宽范围动态阈值配置比较器，实现功率和面积效率的2bit/step操作。通过简单的Vcm偏置电流源配置比较器阈值，ADC对10%的电源变化保持抗扰度。在40nm CMOS中制作的原型ADC在0.5 V单电源电压下以6.14 MS/s的速度实现了44.3 dB SNDR。ADC在0.4V时的峰值FoM为5.9fJ/ convo -step，工作电压降至0.35V。
A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC
An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V.
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