ExCL双极技术发展中的尺度问题

J. Brighton, D. Verret, T.T. Ten Eyck, M.T. Welch, R. E. McMann, M. Torreno, A. Appel, M. Keleher
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引用次数: 7

摘要

讨论了扩展ExCL技术时遇到的几个问题。结果表明,在0.15 μ m基宽以下掺杂谱线缩放会严重限制工艺纬度。结果表明,快速热退火可以显著降低多晶硅发射极电阻。电容计算表明,互连相关的寄生效应在3 μ m间距以下不会缩放,电平内耦合可能是互连缩放的最终限制。最后,ExCL金属化方案被证明可扩展到2 μ m的金属间距。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Scaling issues in the evolution of ExCL bipolar technology
Several issues encountered in scaling ExCL technology are discussed. It is shown that doping profile scaling below 0.15 mu m base width puts severe restrictions on process latitude. It is demonstrated that the polysilicon emitter resistance can be significantly reduced by rapid thermal annealing. Capacitance calculations show that interconnect-related parasitics do not scale below 3 mu m pitch, and intralevel coupling may provide the ultimate limitation of interconnect scaling. Finally, the ExCL metallization scheme is proven to be scalable to 2 mu m metal pitch.<>
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