A very wideband low noise amplifier for cognitive radios

In this paper, a new full on-chip CMOS low-noise amplifier (LNA) topology for the range of 50 MHz to 10 GHz is introduced that has very low power consumption. It exploits the combination of a common-gate (CG) stage for wideband input matching and a common-source (CS) stage for canceling the noise and distortion of CG stage. Moreover the CS stage used both nMOS and pMOS transistors to improve the IIP2. Simulated in a 90 nm RF CMOS technology, the proposed LNA achieves a noise figure of 2.3 dB to 2.8 dB and input return loss (S11) less than −10 dB over whole the bandwidth while consumes only 6 mW from a 1 V power supply. The average of the power gain (S21) is 12 dB. The achieved IIP3 and IIP2 are about −5 dBm and 20 dBm, respectively.