多管交换机网络监控

Marco Chiesa, F. Verdi
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引用次数: 0

摘要

可编程交换机已被广泛用于设计运行在快速数据平面级别的网络监控解决方案,例如,检测重击者,超级传播者,计算流量大小分布及其熵。许多现有的网络监控工作都假设交换机部署了单个内存,每个处理过的数据包都可以访问该内存。然而,高速ASIC交换机越来越多地部署多个独立的管道,每个管道都配备自己的独立存储器,不能被其他管道访问。在这项工作中,我们开始研究在多管道交换机上部署现有的重量级数据平面监控解决方案,其中“流”的数据包可能会在多个管道上传播,即存储到不同的存储器中。我们首先量化了由于在多个管道上分割监测数据结构而导致的精度下降(例如,高达3000倍的流量大小估计平均误差)。然后,我们介绍了PipeCache,这是一个将现有数据平面机制适应多管道交换机的系统,它将每个流量类的所有监控信息仔细存储到一个特定的管道中(而不是在多个管道上复制信息)。PipeCache依赖于将监控信息短暂地存储到每个管道缓存中,然后完全以数据平面速度将这些信息装载到现有数据包上,并传输到正确的管道。我们在ASIC交换机上实现了PipeCache,并使用真实世界的跟踪来评估它。我们表明,现有的数据平面机制在使用PipeCache增强后,可以实现与单管道部署类似的精度级别和内存需求(即,内存需求降低16倍)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Network Monitoring on Multi-Pipe Switches
Programmable switches have been widely used to design network monitoring solutions that operate in the fast data-plane level, e.g., detecting heavy hitters, super-spreaders, computing flow size distributions and their entropy. Many existing works on networking monitoring assume switches deploy a single memory that is accessible by each processed packet. However, high-speed ASIC switches increasingly deploymultiple independent pipes, each equipped with its own independent memory thatcannot be accessed by other pipes. In this work, we initiate the study of deploying existing heavy-hitter data-plane monitoring solutions on multi-pipe switches where packets of a "flow" may spread over multiple pipes, i.e., stored into distinct memories. We first quantify the accuracy degradation due to splitting a monitoring data structure across multiple pipes (e.g., up to 3000x worse flow-size estimation average error). We then present PipeCache, a system that adaptsexisting data-plane mechanisms to multi-pipe switches by carefully storing all the monitoring information of each traffic class into exactly one specific pipe (as opposed to replicate the information on multiple pipes). PipeCache relies on the idea of briefly storing monitoring information into a per-pipe cache and then piggybacking this information onto existing data packets to the correct pipeentirely at data-plane speed. We implement PipeCache on ASIC switches and we evaluate it using a real-world trace. We show that existing data-plane mechanisms achieves accuracy levels and memory requirements similar to single-pipe deployments when augmented with PipeCache (i.e., up to 16x lower memory requirements).
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