基于mips的32位RISC CPU指令解码器模块设计

2009 Second Pacific-Asia Conference on Web Mining and Web-based Application Pub Date : 2009-06-06 DOI:10.1109/WMWA.2009.62

Kui Yi, YueHua Ding

{"title":"基于mips的32位RISC CPU指令解码器模块设计","authors":"Kui Yi, YueHua Ding","doi":"10.1109/WMWA.2009.62","DOIUrl":null,"url":null,"abstract":"In this paper, through analysis of function and working theory of RISC CPU instruction decoder module, we design instruction decoder module of 32-bit CPU. The instruction decoder includes register file¿write back data to register file¿sign bit extend¿relativity check , and it is simulated on QuartusII successfully","PeriodicalId":375180,"journal":{"name":"2009 Second Pacific-Asia Conference on Web Mining and Web-based Application","volume":"237 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"32-bit RISC CPU Based on MIPS-Instruction Decoder Module Design\",\"authors\":\"Kui Yi, YueHua Ding\",\"doi\":\"10.1109/WMWA.2009.62\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, through analysis of function and working theory of RISC CPU instruction decoder module, we design instruction decoder module of 32-bit CPU. The instruction decoder includes register file¿write back data to register file¿sign bit extend¿relativity check , and it is simulated on QuartusII successfully\",\"PeriodicalId\":375180,\"journal\":{\"name\":\"2009 Second Pacific-Asia Conference on Web Mining and Web-based Application\",\"volume\":\"237 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Second Pacific-Asia Conference on Web Mining and Web-based Application\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/WMWA.2009.62\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Second Pacific-Asia Conference on Web Mining and Web-based Application","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WMWA.2009.62","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

本文通过分析RISC CPU指令解码器模块的功能和工作原理，设计了32位CPU的指令解码器模块。该指令解码器包括寄存器文件、回写数据到寄存器文件、符号位扩展、相关性校验，并在QuartusII上进行了成功的仿真

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32-bit RISC CPU Based on MIPS-Instruction Decoder Module Design

In this paper, through analysis of function and working theory of RISC CPU instruction decoder module, we design instruction decoder module of 32-bit CPU. The instruction decoder includes register file¿write back data to register file¿sign bit extend¿relativity check , and it is simulated on QuartusII successfully

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2009 Second Pacific-Asia Conference on Web Mining and Web-based Application

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