{"title":"一种采用不同逻辑风格的4位桶式移位器设计","authors":"Priyanka Tiwari, Amit Kumar","doi":"10.1109/icacfct53978.2021.9837367","DOIUrl":null,"url":null,"abstract":"Very–low-power CMOS IC design is needed for any communication systems. The system’s performance is measured in terms of less power dissipation, small delay and small area. In ALU design we use Shift resisters to perform the addition, multiplications, shifting and floating point arithmetic. Shift resistors are made up of flip flops, in which n clock pulses are required for n shifts. We can use Barrel Shifters instead of shift resistors, which requires only one clock pulse for n shift. In this paper I designed a 4-bit Barrel Shifters using Static CMOS, TGL and PTL. And measured the performance depend on the parameters like delay and power consumed. Analysis is done in cadence virtuoso tool at 45nm technology.","PeriodicalId":312952,"journal":{"name":"2021 First International Conference on Advances in Computing and Future Communication Technologies (ICACFCT)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 4-bit Barrel Shifter Design using Diverse Logic Style\",\"authors\":\"Priyanka Tiwari, Amit Kumar\",\"doi\":\"10.1109/icacfct53978.2021.9837367\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Very–low-power CMOS IC design is needed for any communication systems. The system’s performance is measured in terms of less power dissipation, small delay and small area. In ALU design we use Shift resisters to perform the addition, multiplications, shifting and floating point arithmetic. Shift resistors are made up of flip flops, in which n clock pulses are required for n shifts. We can use Barrel Shifters instead of shift resistors, which requires only one clock pulse for n shift. In this paper I designed a 4-bit Barrel Shifters using Static CMOS, TGL and PTL. And measured the performance depend on the parameters like delay and power consumed. Analysis is done in cadence virtuoso tool at 45nm technology.\",\"PeriodicalId\":312952,\"journal\":{\"name\":\"2021 First International Conference on Advances in Computing and Future Communication Technologies (ICACFCT)\",\"volume\":\"157 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-12-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 First International Conference on Advances in Computing and Future Communication Technologies (ICACFCT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/icacfct53978.2021.9837367\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 First International Conference on Advances in Computing and Future Communication Technologies (ICACFCT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icacfct53978.2021.9837367","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 4-bit Barrel Shifter Design using Diverse Logic Style
Very–low-power CMOS IC design is needed for any communication systems. The system’s performance is measured in terms of less power dissipation, small delay and small area. In ALU design we use Shift resisters to perform the addition, multiplications, shifting and floating point arithmetic. Shift resistors are made up of flip flops, in which n clock pulses are required for n shifts. We can use Barrel Shifters instead of shift resistors, which requires only one clock pulse for n shift. In this paper I designed a 4-bit Barrel Shifters using Static CMOS, TGL and PTL. And measured the performance depend on the parameters like delay and power consumed. Analysis is done in cadence virtuoso tool at 45nm technology.