亚10nm节点高频工作CNFET运放的优化

Md Zubair Ebne Rafique, Alam Mahmud, S. M. Mominuzzaman
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引用次数: 1

摘要

本文对基于碳纳米管场效应晶体管(CNFET)的运放在10nm以下节点的高频工作参数进行了优化。优化了通道长度、栅极氧化物厚度、栅极介电常数、间隔片掺杂、间隔片介电常数和节距等参数。对于运放的高频工作,最佳的CNFET参数为沟道长度10 nm、栅极氧化物介电常数10 nm、栅极氧化物厚度3 nm、节距5 nm、源漏掺杂浓度为零、间隔层氧化物介电常数4。研究了采用这些最优值的CNFET运放的性能,并与以往的工作进行了比较。所得结果显示,先前设计的Si CMOS运算放大器、32nm CNFET和本文研究的sub- 10nm CNFET运算放大器之间存在显著差异。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Optimization of CNFET op amp for high frequency operation in sub-10-nm node
This paper presents optimization of various parameters of carbon nanotube field effect transistor (CNFET) based op amp in sub-10 nm node for high frequency operation. Parameters such as, channel length, gate oxide thickness, gate dielectric constant, spacer doping, spacer dielectric constant and pitch, are optimized. For high frequency operation of op amp, optimum values of CNFET parameters are found to be 10 nm channel length, 10 dielectric constant of gate oxide, 3 nm gate oxide thickness, 5 nm pitch, zero source/drain doping concentration, 4 dielectric constant of spacer oxide. Performance of CNFET op amp incorporating these optimum values is investigated and compared with previous work. Obtained results reveals significant differences among previously designed Si CMOS op amp, 32 nm CNFET and the sub-10-nm CNFET op amp investigated here.
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