用于逻辑分辨率子集的高速硬件单元

[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21 Pub Date : 1988-01-03 DOI:10.1145/62504.62542

D. Wong

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引用次数: 0

摘要

用于逻辑编程的高速引擎一直是最近许多研究的目标。在这里，我们提出了一个高级硬件设计及其自定义数据格式，用于直接执行逻辑解析的子集。这种设计在统一参数和替换变量绑定时使用并行性，这与广泛讨论的OR和and并行性不同。

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A High-speed Hardware Unit For A Subset of Logic Resolution

High-speed engines for logic programming have been the target of much recent research. Here, we present a high-level hardware design and its custom data formats for directly performing a subset of logic resolution. This design uses parallelism in unifying arguments and substituting variable bindings which is distinct from the widely discussed OR and AND parallelism.

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[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21

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