一个0.08 /spl mu/m/sup 2/大小的8F/sup 2/堆叠DRAM单元，用于千兆位DRAM

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI:10.1109/VLSIT.2002.1015386

Hyunpil Noh, Suock Jeong, Seongjoon Lee, Yousung Kim, Woncheol Cho, M. Huh, G. Jeong, J. Suh, Hoyeop Kweon, J. Roh, Kisoo Shin, Sangdon Lee

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引用次数: 1

摘要

第一个尺寸为0.08 /spl mu/m/sup 2/的8F/sup 2/堆叠DRAM单元已成功集成，采用多插头方案进行着陆插头触点和W/多栅极和Ru MIM电容器，该单元在易于功能检查模式下工作已被证明。采用W栅极技术的电池晶体管具有/spl sim/40 /spl mu/A的饱和电流(I/sub OP/)，阈值电压(V/sub tsat/)为0.9 V，令人满意的环形振荡器延迟特性为/spl sim/50 ps。

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A 0.08 /spl mu/m/sup 2/-sized 8F/sup 2/ stack DRAM cell for multi-gigabit DRAM

The first 8F/sup 2/ stack DRAM cell with 0.08 /spl mu/m/sup 2/ size has been successfully integrated by employing a poly plug scheme for landing plug contacts and W/poly gates and Ru MIM capacitors, of which cell working has been proven under easy function check mode. The cell transistor with W gate technology exhibits sufficient saturation current (I/sub OP/) of /spl sim/40 /spl mu/A with threshold voltage (V/sub tsat/) of 0.9 V and satisfactory ring oscillator delay characteristics of /spl sim/50 ps.

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2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

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