Z. M. Hussain, B. Boashash, M. Hassan-Ali, S. Al-Araji
{"title":"一个延时数字锁环","authors":"Z. M. Hussain, B. Boashash, M. Hassan-Ali, S. Al-Araji","doi":"10.1109/ISSPA.1999.818194","DOIUrl":null,"url":null,"abstract":"A digital tanlock loop (DTL) that utilises a constant time-delay unit instead of the constant 90/spl deg/ phase-shifter is proposed to reduce the complexity of implementation and rid the circuit of the practical problems, approximations and limitations caused by the 90/spl deg/ phase-shifter. The time-delay digital tanlock loop (TDTL) preserves the most important features of the conventional DTL (CDTL) and introduces improvement over the first-order CDTL under suitable choice of the circuit parameters.","PeriodicalId":302569,"journal":{"name":"ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications (IEEE Cat. No.99EX359)","volume":"211 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"60","resultStr":"{\"title\":\"A time-delay digital tanlock loop\",\"authors\":\"Z. M. Hussain, B. Boashash, M. Hassan-Ali, S. Al-Araji\",\"doi\":\"10.1109/ISSPA.1999.818194\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A digital tanlock loop (DTL) that utilises a constant time-delay unit instead of the constant 90/spl deg/ phase-shifter is proposed to reduce the complexity of implementation and rid the circuit of the practical problems, approximations and limitations caused by the 90/spl deg/ phase-shifter. The time-delay digital tanlock loop (TDTL) preserves the most important features of the conventional DTL (CDTL) and introduces improvement over the first-order CDTL under suitable choice of the circuit parameters.\",\"PeriodicalId\":302569,\"journal\":{\"name\":\"ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications (IEEE Cat. No.99EX359)\",\"volume\":\"211 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-08-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"60\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications (IEEE Cat. No.99EX359)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSPA.1999.818194\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications (IEEE Cat. No.99EX359)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSPA.1999.818194","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A digital tanlock loop (DTL) that utilises a constant time-delay unit instead of the constant 90/spl deg/ phase-shifter is proposed to reduce the complexity of implementation and rid the circuit of the practical problems, approximations and limitations caused by the 90/spl deg/ phase-shifter. The time-delay digital tanlock loop (TDTL) preserves the most important features of the conventional DTL (CDTL) and introduces improvement over the first-order CDTL under suitable choice of the circuit parameters.