一个ASIC-Ready 1.25-6.25Gb /s SerDes, 90nm CMOS，具有多标准兼容性

2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI:10.1109/ASSCC.2008.4708723

Y. Nishi, K. Abe, J. Ribo, B. Roederer, A. Gopalan, M. Benmansour, A. Ho, A. Bhoi, M. Konishi, R. Moriizumi, V. Pathak, S. Gondi

{"title":"一个ASIC-Ready 1.25-6.25Gb /s SerDes, 90nm CMOS，具有多标准兼容性","authors":"Y. Nishi, K. Abe, J. Ribo, B. Roederer, A. Gopalan, M. Benmansour, A. Ho, A. Bhoi, M. Konishi, R. Moriizumi, V. Pathak, S. Gondi","doi":"10.1109/ASSCC.2008.4708723","DOIUrl":null,"url":null,"abstract":"A small area PHY transceiver that is compatible with CE16G-LR, CE16G-SR, SAS-6G, PCle and XAUl standards is demonstrated. The 4-channel transceiver is realized in a 90 nm CMOS process with each channel occupying a die area of 0.325 mm2. Power dissipation per channel is less than 230 mW from a 1V supply for 6.25 Gb/s, and scales for data rates down to 1.25 Gb/s.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"An ASIC-Ready 1.25–6.25Gb/s SerDes in 90nm CMOS with multi-standard compatibility\",\"authors\":\"Y. Nishi, K. Abe, J. Ribo, B. Roederer, A. Gopalan, M. Benmansour, A. Ho, A. Bhoi, M. Konishi, R. Moriizumi, V. Pathak, S. Gondi\",\"doi\":\"10.1109/ASSCC.2008.4708723\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A small area PHY transceiver that is compatible with CE16G-LR, CE16G-SR, SAS-6G, PCle and XAUl standards is demonstrated. The 4-channel transceiver is realized in a 90 nm CMOS process with each channel occupying a die area of 0.325 mm2. Power dissipation per channel is less than 230 mW from a 1V supply for 6.25 Gb/s, and scales for data rates down to 1.25 Gb/s.\",\"PeriodicalId\":143173,\"journal\":{\"name\":\"2008 IEEE Asian Solid-State Circuits Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2008.4708723\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2008.4708723","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 14

摘要

演示了一种兼容CE16G-LR、CE16G-SR、SAS-6G、PCle和XAUl标准的小面积PHY收发器。该4通道收发器采用90nm CMOS工艺实现，每个通道占用0.325 mm2的芯片面积。在1V电源下，每通道功耗小于230 mW，传输速率为6.25 Gb/s，数据速率可降至1.25 Gb/s。

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An ASIC-Ready 1.25–6.25Gb/s SerDes in 90nm CMOS with multi-standard compatibility

A small area PHY transceiver that is compatible with CE16G-LR, CE16G-SR, SAS-6G, PCle and XAUl standards is demonstrated. The 4-channel transceiver is realized in a 90 nm CMOS process with each channel occupying a die area of 0.325 mm2. Power dissipation per channel is less than 230 mW from a 1V supply for 6.25 Gb/s, and scales for data rates down to 1.25 Gb/s.

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2008 IEEE Asian Solid-State Circuits Conference

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