Jea-Chun Lee, Y. Huh, Jau-Wen Chen, P. Bendix, S. Kang
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引用次数: 25
摘要
本文提出了一种用于多功率集成电路中充电器件模型(CDM)失效分析的芯片级仿真方法。提出了一种考虑CDM失效和有效仿真的电路模型,并将其与电路级ESD模拟器iETSIM相结合。分析了多功率集成电路中的CDM行为,并通过芯片级仿真预测了CDM应力的易损点。仿真结果通过0.25 /spl μ m CMOS ASIC的CDM测试得到验证,具有良好的相关性。这种全芯片级的仿真方法使我们能够在详细的芯片平面图和电网网络开始之前解决CDM故障问题。
Chip-level simulation for CDM failures in multi-power ICs
This paper presents a new chip-level simulation methodology for charged-device model (CDM) failure analysis in multi-power ICs. A circuit model considering reported CDM failures and efficient simulation is proposed and incorporated with the circuit-level ESD simulator, iETSIM. The CDM behaviors in multi-power ICs are analyzed and the vulnerable sites to CDM stress can be predicted by chip-level simulation. Simulation results are verified by CDM testing of a 0.25 /spl mu/m CMOS ASIC and show good correlation. This simulation methodology at the full-chip level enables us to address CDM failure issues before the detailed chip floorplan and power grid networking are started.