VLSI设计中的集成互连电路建模

W. Jung, Ghun-Up Cha, Young-Bae Kim, J. Baek, Choon-Kyung Kim
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引用次数: 2

摘要

开发了一个集成的互连建模系统SIMS,实现了互连的参数化建模,并提供了原理图采集和编辑接口。SIMS根据技术工程师的指示自动驱动数字互连仿真,为互连寄生体创建多项式模型库,生成包含互连结构SPICE模型的网表,自动驱动电路仿真并通过高级GUI显示仿真结果。基于SIMS的VLSI设计使得快速准确地考虑寄生效应成为可能,这在深亚微米电路设计中变得更加重要。利用这种能力,可以实现具有优化互连布局的电路设计。最终,通过建立可制造性设计的概念,集成系统有助于降低技术开发的成本和上市时间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Integrated interconnect circuit modeling for VLSI design
An integrated interconnect modelling system, SIMS, is developed with parametrized modeling of interconnect and an interface with schematic capture and editor. SIMS automatically drives numerical interconnect simulation as directed by technology engineers, creates a polynomial model library for interconnect parasitics, generates a netlist including the SPICE model for the interconnect structure, automatically drives circuit simulations and displays the simulation results through an advanced GUI. VLSI design with SIMS makes it possible to consider parasitic effects fast and accurately, which becomes more important in deep submicron circuit design. With this capability, circuit design with optimized interconnect layout can be achieved. Ultimately, the integrated system helps to reduce the cost of technology development and the time to market by building up the concept of design for manufacturability.
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