带电流模式反馈缓冲放大器的低1/f噪声CMOS低压差稳压器

W. Oh, B. Bakkaloglu, B. Aravind, Siew Kuok Hoon
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引用次数: 10

摘要

低噪声、低差(LN-LDO)稳压器对于深亚微米模拟基带和射频片上系统设计的电源调节至关重要。提出了一种利用斩波稳定误差放大器的低1/f噪声LDO稳压器。为了实现负载瞬态的快速响应,设计了非对称输入对的电流型反馈放大器(CFA)作为第二级。斩波频率高达1MHz,在100kHz时可实现32nV/radicHz的输出噪声谱密度和38dB的PSR。与等效噪声密度的静态调节器相比,误差放大器的硅面积减少了75%。与同等功耗的电压模式缓冲器相比,电流模式反馈第二级缓冲器的稳定时间减少了60%,在50mA负载阶跃下达到0.6 μ c的稳定时间。LN-LDO采用0.25 μ m CMOS工艺设计和制造,具有五层金属,占地0.88mm2
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Low 1/f Noise CMOS Low-Dropout Regulator with Current-Mode Feedback Buffer Amplifier
Low-noise, low-dropout (LN-LDO) regulators are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. A low 1/f noise LDO regulator utilizing a chopper stabilized error amplifier is presented. In order to achieve fast response during load transients, a current-mode feedback amplifier (CFA) with an asymmetrical input pair is designed as a second stage. With chopping frequencies up to 1MHz, an output noise spectral density of 32nV/radicHz and PSR of 38dB is achieved at 100kHz. Compared to an equivalent noise density static regulator, the error amplifier silicon area is reduced by 75%. With the current-mode feedback second stage buffer, settling time is reduced by 60% in comparison to an equivalent power consumption voltage mode buffer, achieving 0.6musec settling time for a 50mA load step. The LN-LDO is designed and fabricated on a 0.25 mum CMOS process with five layers of metal, occupying 0.88mm2
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