Coupling aware power estimation for on-chip VLSI distributed RLCG global interconnects using model order reduction technique

In this paper, we have derived a closed form formula for the power dissipation in highly coupled distributed RLCG interconnects taking the mutual inductive coupling into account. Power is increasingly becoming the bottleneck for the design of high performance VLSI circuits. It is essential to analyze how the various components of power are likely to scale in the future, thereby identifying the key problematic areas. While most of the analysis focus on the timing aspects of interconnects, power consumption is also an important issue to be addressed and modeled accurately. In this paper, estimation of the power dissipation of interconnects is studied using a reduced-order model. The relation between power consumption and the poles and residues of a transfer function is derived, and an appropriate driver model is developed, allowing power consumption to be computed efficiently. The results obtained from SPICE and from that of using our approach, justify the accuracy and the effectiveness of our proposed model.