用于GaAs DCFL时序分析的延迟宏模型

Proceedings EURO-DAC '92: European Design Automation Conference Pub Date : 1992-11-01 DOI:10.1109/EURDAC.1992.246251

A. Kayssi, K. Sakallah

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引用次数: 2

摘要

推导了砷化镓直接耦合FET逻辑(GaAs DCFL)电池的时序宏模型。它计算一个单元的延迟作为诸如晶体管尺寸、电容负载、风扇输出和输入开关时间等参数的函数。基于推导出的宏模型的计算结果与电路仿真结果非常吻合，计算时间节省了两到三个数量级。

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Delay macromodels for the timing analysis of GaAs DCFL

A timing macromodel for gallium arsenide direct-coupled FET logic (GaAs DCFL) cells is derived. It calculates the delay of a cell as a function of such parameters as transistor sizes, capacitive loading, fanout, and input switching time. Calculations based on the derived macromodel show excellent agreement with circuit simulation at two to three orders of magnitude savings in computation time.<>

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Proceedings EURO-DAC '92: European Design Automation Conference

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