Hot carrier degradation and ESD in submicron CMOS technologies: how do they interact?

In this paper, the phenomenon of channel hot carrier (CHC) induced degradation in transistors and its relation to ESD reliability is reviewed. The principles of CHC and the trade-off with ESD during technology development from channel/drain engineering, including consideration for mixed voltage designs, are discussed. Also, latent damage due to ESD-induced effects on CHC are considered. Finally, it is shown how the generation of hot carriers can help in the optimization of the performance of advanced ESD protection concepts.